随着工艺节点的进步,SRAM中静态功耗占整个功耗的比例越来越大,纳米尺度的IC设计中,漏电流是一个关键问题.为了降低SRAM静态功耗,本文提出一种字线负偏压技术,并根据不同的工艺角,给出最合适的负偏压大小,使得SRAM漏电流得到最大程度的降低.仿真结果表明,SMIC 40nm工艺下,和未采用字线负偏压技术的6管SRAM存储单元相比,该技术在典型工艺角下漏电流降低11.8%,在慢速工艺角下漏电流降低能到达29.1%.%With the development of semiconductor manufacturing technology , SRAM static power consumption in the proportion of the total power consumption is more and more serious. Leakage is a key issue in the nanoscale IC design. In order to reduce the static power consumption of SRAM , this paper proposes a negative word line technique , and gives the most appropriate negative bias voltage under different corners, which can lead to a maximum decrease of cell leakage.The simulation results show that under the SMIC 40 nm process, the technology can reduce 11.8% in the typical corner, and 29.1% in SNSP corner, comparing 6T-SRAM without this technology.
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